Modern microprocessors are highly complex. They usually include multiple components that are capable of executing multiple tasks at very high speed. Many modern devices usually include one or more processors, controllers and various memory modules, including cache memories.
Various systems and methods are known for extracting information that can reflect that manner in which computerized systems operate. These apparatuses include on-chip debuggers, on chip emulators and the like.
The IEEE-ISTO 5001™ standard, also known as NEXUS defines a standard debug interface for embedded control applications. NEXUS provides a relatively limited amount of de-bugging information but is capable of controlling the processor. The tracked information can be transmitted via dedicated I/O pins or via the JTAG interface, but this is not necessarily so.
The following U.S. patents and U.S. patent application, all incorporated herein by reference, provide an example of some state of the art debugging and emulation apparatuses and methods: U.S. Pat. No. 653,338 of Smolders, titled “System for tracing hardware counters utilizing programmed trace interrupt after each branch instruction or at the end of each code basic block”; U.S. patent application 2002/0049893 of Williams et al., titled “Accessing diagnostic program counter value data within data processing system”; U.S. Pat. No. 6,615,370 of Edwards et al., titled “Circuit for storing trace information”, and U.S. Pat. No. 6,134,676 of VanHuben et al., titled “Programmable hardware event monitoring method”.
There is a need to provide a large amount of information representing the behavior of complex processor based systems, and especially of providing information about events that are related to each other.
There is a need to provide trace information in addition to information required by known standards, without preventing the provision of standard trace information over standardized interfaces.